SMD ULTRA LOW POWER OSCILLATORS|SMD Silicon Oscillators|Waveform V.1|Waveform V.1 (2)|LVCMOS AND SOFTLEVEL OUTPUTS. VDD=3.3V|HARMONIC ATTENUATION

HOW SMD SILICON CLOCK OSCILLATOR SIGNIFICANTLY IMPROVES EMV

Every product designer has to deal with the issue of electromagnetic compatibility (EMC) on a daily basis - especially when frequency-determining components such as crystal oscillators are used. The ICs used in commercially available quartz oscillators generate steep edges and produce harmonics. Although spread spectrum oscillators are available, they cannot be used in many applications as they are too imprecise. With a centre spread of ±0.5%, for example, the output frequency is modulated in a range of fout ±0.5%. Based on a frequency of 33.333 or 66.666 MHz, the frequency modulation of ±0.5% would correspond to a frequency modulation range of 33.333 MHz ±166.665 kHz or 66.666 MHz ±333.330 kHz - too much for accurate clocking. In most cases, only ±50 ppm is permissible in these applications, i.e. 100 times less. A frequency stability of ±50ppm corresponds to a tolerance of ±1.66665 kHz at 33.333 MHz and a tolerance of ±3.3333 kHz at 66.666 MHz. In such cases, developers previously had to try to reduce the EMC using very expensive measures. This is no longer necessary. Based on innovative IC technology, Next Generation Clocking, Petermann-Technik from Landsberg am Lech offers a wide range of SMD silicon clock oscillators with a SoftLevel output signal. SoftLevel technology is a programmable output signal in which the harmonics of an LVCOMS output signal can be significantly reduced by increasing the rise (trise) and fall time (tfall). Thanks to SoftLevel technology, the output signal can be precisely adapted to the customer's requirements.

[caption id="attachment_147" align="alignleft" width="300"] Figure 1: Period duration t of an LVCMOS output signal with trise and tfall between 20% and 80%[/caption] .

What the SoftLevel function does

Figure 1 shows the period duration t of an LVCMOS output signal withtrise and tfall between 20% and 80%, Figure 2 shows the edge curve of a normal LVCMOS square wave signal (red line) compared to the SoftLevel LVCMOS output signal (blue line) with the supply voltage of +3.3 VDC. It can be clearly seen that the SoftLevel function rounds off the edges of the square wave signal (shape similar to a shark fin) and thus significantly reduces the harmonics. Figure 3 shows the EMC attenuation (odd harmonics) in relation to the period duration t of the output signal.trise and tfall are expressed in relation to the period duration t of the clock signal. Here,trise and tfall can be extended in the range from 0.05 to 0.45 (5% to 45%) of t. Iftrise and tfall are extended by 5% compared to the base signal, the signal shape comes fairly close to the original rectangular signal. With an extension of up to 45%, the shape of the output signal increasingly resembles a shark fin and the EMC attenuation is over -60 dB at the 11th harmonic. An enormous value for such a simple adjustment of thetrise and tfall.

[caption id="attachment_148" align="alignleft" width="397"] Figure 2: Edge curve of a normal LVCMOS square wave signal (red line) compared to a soft-level LVCMOS output signal (blue line) with rounded edges[/caption] .

What does the SoftLevel function cost the developer?

Nothing, because the SoftLevel function is a standard feature of the SMD silicon clock oscillators of the LPO, LPOP, HTLPO, WTLPO, UPO, HTLPO-AUT and WTLPO-AUT series. (AUT = Automotive based on AEC-Q100). In addition, these oscillator series are available in standard housings with dimensions of 7 mm x 5 mm, 5 mm x 3.2 mm, 3.2 mm x 2.5 mm, 2.5 mm x 2.0 mm and 2.0 mm x 1.6 mm and can therefore be fitted to existing PCB layouts and thus directly replace quartz oscillators. In order for PETERMANN-TECHNIK's in-house engineering department to be able to provide customers with optimum advice and programme a product based on their application requirements, the developer must specify the trise/fall time they can accept in their application. By programming - extending the trise/fall time - the attenuation of the odd harmonics is achieved. In the circuit design for the SMD silicon clock oscillators, the specialists at Petermann-Technik recommend the use of a decoupling capacitance of 0.1 µF between the supply voltage and ground pins. This significantly minimises the effects of the supply voltage fed in.

[caption id="attachment_149" align="alignleft" width="300"] Figure 3: EMC reduction in relation to the longer period duration[/caption] .

Further advantages of SMD silicon clock oscillators

The SMD silicon clock oscillators of the above-mentioned series are also available with a supply voltage range of 2.25 to 3.63 VDC. Within thisVDD range, the oscillators can be operated with any supply voltage (e.g. 2.5 VDC±10%, 2.8 VDC±10%, 3.0 VDC±10%or 3.3 VDC ±10%). This means that the product developer only has to qualify one oscillator for four classic supply voltages. This standard feature saves the developer a lot of money in component qualification and the supply chain manager a lot of money in the procurement, administration and storage of significantly fewer components. Larger quantities of a component also result in a more favourable price. Of course, the SoftLevel function described above is also available as a standard feature for the VVDD range from 2.25 to 3.63 VDC.

In addition, the SMD silicon clock oscillators have very precise frequency tolerances as standard, for example ±20ppm@-40/85 °C, ±30ppm@-40/105 °C and ±50ppm@-40/125 °C. Of course, AEC-Q100-compatible oscillators (HTLPO-AUT and WTLPO-AUT) with all the features described are also available.

SoftLevel function improves EMC behaviour

The EMC behaviour of SMD clock oscillators can be significantly improved with the SoftLevel function by simply adjusting thetrise and tfall of the output signal free of charge, so that the developer no longer has to take expensive measures to improve the EMC behaviour of his application. The SMD silicon clock oscillators can be fitted to existing PCB layouts immediately. Thanks to the VDD range of 2.25 to 3.63 VDC and the very tight standard frequency tolerances, a great deal of money can also be saved in component qualification, procurement, management and storage.

Further information can be found at:

Silicon oscillators (like MEMS)

or

Silicon Oscillators Product Overview

Technical questions:

Phone: 0 81 91 / 30 53 95

E-mail: info@petermann-technik.de

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