Output signals from quartz oscillators

Quartz oscillators generate highly stable clock signals that are required in almost all electronic systems - from simple microcontroller circuits to high-speed data transmission systems.

The output signal of an oscillator must match the downstream logic family or interface. Over the decades, various output standards have evolved, each tailored to the requirements of its time and application.

This document provides a comprehensive overview of the seven most common output signal types for crystal oscillators: CMOS, TTL, Clipped Sine Wave, Sine Wave, LVPECL, LVDS and HCSL.

For each type, the historical development, the electrical properties, the typical signal form and the preferred areas of application are explained.

The development of output signal types can be closely linked to the evolution of semiconductor technology and the increasing demands on clock frequencies and signal integrity:

2.1 TTL (transistor-transistor logic) - from around 1964

TTL was one of the first widely used digital logic standards and was introduced by Texas Instruments as the 7400 series. Oscillators with TTL output operate with a supply voltage of 5 V and provide level ranges that are directly compatible with TTL gates. The standard characterised digital electronics for decades and was the dominant logic standard until the 1990s.

2.2 CMOS (Complementary Metal-Oxide-Semiconductor) - from around 1968

CMOS technology was originally developed by RCA and is characterised by extremely low quiescent current consumption. CMOS oscillators provide rail-to-rail output signals, i.e. the output oscillates almost between 0 V and VCC. With advancing miniaturisation and the trend towards lower supply voltages (3.3 V, 2.5 V, 1.8 V), CMOS has become the most widely used output standard for crystal oscillators.

2.3 Sine wave - since the early days of oscillator technology

Sinusoidal output signals are as old as oscillator technology itself. Quartz oscillators physically oscillate sinusoidally; all other signal forms are only generated by downstream circuits. Sine wave outputs are preferably used in high-frequency technology, in measuring devices and in analogue signal processing, as they do not generate harmonics.

2.4 Clipped sine wave - from around the 1970s

The clipped sine wave output is a compromise between a sine wave and a square wave output. The sine wave signal is limited (clipped) at the peaks, resulting in steeper edges than with a pure sine wave, but fewer harmonics than with a square wave signal. This type of output was used particularly in telecommunications and in older high-frequency applications. Today, clipped sine wave ICs are still mainly used in TCXOs. With this technology, significantly more energy-efficient TCXOs can be constructed than with CMOS technology. CSW TCXOs are therefore used as a reference in navigation devices, emergency call systems and gateways. Wherever signal range (radio) and high-precision positioning are required.

2.5 LVPECL (Low-Voltage Positive Emitter-Coupled Logic) - from the 1990s onwards

With the need for ever higher clock frequencies in network and telecommunication systems, LVPECL emerged as a fast differential output logic. LVPECL is based on the classic ECL technology (emitter-coupled logic), which was developed back in the 1960s for high-speed applications, and adapts it for lower supply voltages (3.3 V instead of -5.2 V). LVPECL offers extremely short switching times and is suitable for frequencies of well over 1 GHz.

2.6 LVDS (Low-Voltage Differential Signalling) - from 1994

LVDS was introduced in 1994 as the ANSI/TIA/EIA-644 standard and optimises differential signal transmission for low power consumption and high data rates. The low differential voltage swing of only 350 mV enables fast switching operations with minimal electromagnetic radiation. LVDS is widely used today in display interfaces, serial data links and FPGA blocking.

2.7 HCSL (High-Speed Current Steering Logic) - from around 2002

HCSL was specially developed for the PCI Express standard and has been the reference clock standard since the first PCIe generation. The PCI-SIG specified HCSL as a current-mode-based differential signal with a very low voltage swing, optimised for the 100 MHz reference clocks in PCIe systems. Today, HCSL is indispensable in every PC, server and embedded system with a PCIe interface.

The following diagrams show the idealised signal characteristics of the seven output types. Note the different voltage ranges and oscillation deviations - these are crucial for compatibility with downstream receivers.

3.1 CMOS

The CMOS signal is characterised by its full voltage swing between GND and VCC. The input thresholds VIL and VIH are typically 30 % and 70 % of VCC respectively, which ensures a wide signal-to-noise ratio. The symmetrical output driver structures (P-channel/N-channel MOSFET) enable almost identical rise and fall times.

3.3 Clipped Sine Wave

In contrast to the CMOS output, TTL does not reach rail-to-rail levels. The high level (VOH) is typically 3.4 V (minimum 2.4 V), the low level (VOL) a maximum of 0.4 V. The asymmetrical thresholds (VIL = 0.8 V, VIH = 2.0 V) result from the bipolar transistor architecture. The so-called "forbidden range" between 0.8 V and 2.0 V must not be assumed in static operation.

3.3 Clipped Sine Wave

With the clipped sine wave output, the natural sine wave signal of the quartz resonator is limited at defined threshold values. The dashed line shows the unclipped sine wave. Clipping results in steeper zero crossings than with a pure sine wave, which makes it easier to control subsequent logic, while the harmonic content remains moderate.

3.4 Sine wave

The sine wave output provides the cleanest spectrum of all output forms: ideally only a single spectral line at the fundamental frequency. The amplitude is specified as peak-to-peak voltage (Vpp) or as power in dBm. Typical values are 0.5 to 1.0 Vpp or 0 to +13 dBm in 50 Ω systems.

3.5 LVPECL

LVPECL uses differential signal routing: two complementary outputs (Q and Q̅) oscillate in antiphase around a common common mode level (VCM), which is typically VCC-1.3 V. The differential voltage swing is approx. 800 mV. The current source architecture enables extremely fast switching times with minimal overshoot.

3.6 LVDS

LVDS is characterised by its particularly low differential voltage swing of only 350 mV. The common mode level is 1.25 V. The current-controlled driver (typically 3.5 mA) and the 100 Ω termination ensure high signal integrity with minimum power consumption. The low amplitude minimises electromagnetic radiation.

3.7 HCSL

HCSL operates with a very low voltage swing: VOH is typically 0.74 V and VOL 0.17 V, resulting in a common mode level of approx. 0.45 V. The current control architecture is specially optimised for the requirements of the PCIe specification and allows precise impedance matching via 50 Ω terminations to ground.

The following table summarises the main properties of all seven output types:

5.1 Single-ended vs. differential

The most fundamental difference between the output types is the signal routing. CMOS, TTL, clipped sine wave and sine wave are single-ended signals - they reference a common ground. LVPECL, LVDS and HCSL, on the other hand, are differential signals with two complementary lines. Differential signals offer decisive advantages at higher frequencies: they suppress common mode interference, enable smaller voltage deviations and therefore allow faster switching times with less electromagnetic radiation.

5.2 Voltage swing and signal-to-noise ratio

With its rail-to-rail output, CMOS offers the largest absolute voltage swing and therefore the best static signal-to-noise ratio. TTL has a more limited signal-to-noise ratio due to the asymmetrical levels. The differential standards (LVPECL, LVDS, HCSL) compensate for their smaller voltage deviations through the common mode rejection of differential transmission, which means that they often work more reliably in disturbed environments than single-ended signals.

5.3 Power consumption

CMOS oscillators consume almost no current in the static state; the consumption increases proportionally to the frequency (dynamic power dissipation). TTL has a constantly higher quiescent current consumption due to the bipolar architecture. LVPECL requires external terminating resistors and has the highest current consumption of the differential standards. LVDS is known for its low current consumption (typically 3.5 mA driver current). HCSL lies between LVDS and LVPECL in terms of power consumption.

5.4 Frequency range and main applications

For frequencies up to around 200 MHz, CMOS oscillators are the first choice in most cases due to their versatility, simple circuit design and wide availability. From about 200 MHz, differential outputs are recommended. LVPECL offers the highest frequencies (>3 GHz) and is used in networking and telecoms equipment. LVDS covers a wide mid-range and is particularly common in FPGA and display applications. HCSL is optimised for its niche application: the 100 MHz reference clock for PCI Express.

5.5 Termination and circuit complexity

CMOS and TTL outputs generally do not require external termination for short cable lengths - this makes them particularly easy to use. LVPECL requires mandatory external termination resistors (typically: Thevenin termination to VCC-2 V or resistors to ground), which increases the circuit complexity. LVDS is terminated with a 100 Ω differential resistor at the receiver as standard. HCSL uses 50 Ω resistors to ground at each output.

6.1 What are overshoots?

Overshoot and undershoot are short-term voltage peaks that occur during fast switching operations. With a rising edge, the voltage shoots briefly above VCC (overshoot), with a falling edge briefly below GND (undershoot). This is often followed by damped oscillations, which are referred to as "ringing".

The cause lies in the combination of the very steep switching edges of the output driver and the parasitic inductances and capacitances of the conductor track, the housing and the load capacitance. From a physical point of view, a resonant circuit is created from the line inductance and the input capacitance of the receiver. The steeper the switching edge and the longer the conductor track, the more pronounced the overshoot.

6.4 Overshoot with single-ended signals

CMOS: Most affected. The symmetrical P/N-channel MOSFET drivers generate very steep edges which, in combination with line inductances, cause pronounced overshoots. Particularly with modern low-voltage CMOS oscillators (1.8 V), the overshoots relative to the supply voltage can be significant.

TTL: Also susceptible, but for slightly different reasons. The asymmetrical totem-pole output stage generates a short current spike on the rising edge if both transistors are conducting at the same time (cross-conduction). The typically somewhat slower edges compared to modern CMOS mitigate the problem slightly.

Clipped Sine Wave: Significantly less susceptible. Due to the limited amplitude peaks and the comparatively soft edges, there is considerably less high-frequency energy that could stimulate reflections and ringing. The clipping acts as a natural amplitude limiter that suppresses overshoots in the signal.

Sine wave: Practically immune to classic overshoots. As the signal does not contain any abrupt edge transitions, no broadband energy pulse is generated that could excite line resonances. However, impedance mismatches can cause standing waves and reflections that change the signal amplitude at certain points. This is controlled via classic RF termination (50 Ω or 75 Ω termination).

6.5 Overshoots with differential signals

LVPECL: Inherently well suppressed thanks to the current source output stage. The current control naturally limits the maximum edge steepness. However, reflections can still occur if the termination is insufficient, as LVPECL operates at very high frequencies. The correct thevenin or emitter follower circuit is crucial here - not primarily because of overshoots, but to ensure the correct operating point and avoid reflections.

LVDS: Very robust by design. The current-controlled driver supplies a constant current of typically 3.5 mA to the 100 Ω differential termination, which physically limits the voltage swing. Even with impedance discontinuities, reflections remain small, as the low voltage swing of only 350 mV provides little energy for interference. LVDS is one of the most favourable standards in terms of signal integrity.

HCSL: Behaves similarly to LVDS due to its current-based architecture. The very low voltage swing and the 50 Ω termination to ground ensure clean impedance matching. In the PCIe specification, the permissible overshoots are explicitly defined and tightly tolerated, so that HCSL-compliant oscillators already fulfil these requirements by default.

6.6 Countermeasures to control overshoots

The most effective measure for single-ended signals (especially CMOS and TTL) is a series resistor directly at the output of the oscillator, typically in the range of 22 to 47 Ω. Together with the line impedance, this resistor forms a voltage divider that dampens the edge and absorbs reflections. The optimum value results from the difference between the line impedance and the output impedance of the driver.

In addition, short, impedance-controlled traces, minimisation of vias on the clock line, a continuous ground plane under the signal line and sufficient decoupling capacitors close to the oscillator (typically 100 nF ceramic plus 10 µF) also help. Some CMOS oscillator manufacturers also offer models with controlled edge steepness (slew rate control), which already mitigate the problem in the driver.

For differential signals (LVPECL, LVDS, HCSL), correct termination in accordance with the specification is the most important measure. In addition, the two lines of a differential pair should always be routed with the same length and closely coupled in order to minimise skew (runtime differences) and maintain common mode rejection.

The choice of the right output type depends on four main factors: the required clock frequency, the logic family of the receiver, the available power budget and the signal integrity requirements.