Pierce oscillator: Dimensioning, load capacity and EMC optimisation
1 Introduction and objective
Oscillating crystals (quartz resonators) are the preferred frequency reference element in a wide range of applications. Their excellent frequency stability and small size make them indispensable - provided that the surrounding circuitry is correctly dimensioned.
This application note deals with the practical wiring of MHz oscillating crystals in a classic Pierce oscillator circuit.
The focus is on
Function and selection of the serial resistor R_S
Calculation and selection of the load capacitances C1 / C2
Ensuring reliable transient response under all operating conditions
EMC optimisation in accordance with CISPR 25 - reduction of harmonic emissions
2 Problem definition
This application note deals specifically with a 40 MHz fundamental crystal in a 3.2x2.5mm/4pad ceramic housing with a load capacitance of 12 pF. The operating temperature range is -40/+125°C, or the ESR max. 35 Ohm (-40/+125°C) for this AEC-Q200 compatible LOW ESR 40 MHz crystal. The frequency tolerance of the crystal was specified with ±10ppm at +25°C, and a temperature stability of ±50 ppm over the temperature range of -40/+125°C.
During the development of a new automotive application, the customer found that the emission measurement in accordance with CISPR-25 revealed that the limit value was exceeded at approx. 360 MHz, which may be related to the oscillator crystal.
The oscillator circuit contains a parallel resistor of 1 Mohm, as well as a serial resistor and two capacitors of 12pF to GND each.
Question from the customer: How must he dimension the R_S so that there is no more EMC interference and what else must he pay attention to with regard to frequency accuracy and transient behaviour of the 40 MHz oscillating quartz crystal?
3 Basics of the Pierce oscillator
3.1 Circuit topology
The Pierce oscillator consists of four core components:
Component
Function
CMOS inverter
Voltage amplifier with inverting characteristic; supplies the negative resistance R_neg
R_P (1 MΩ)
Parallel resistor; sets the DC operating point of the inverter, forces linear operation at startup
Form the phase shifter network with the quartz oscillator; determine the effective load capacitance C_L
Quartz
High-quality series resonance; oscillates parallel to the specified load capacitance CL
3.2 Oscillation condition (Barkhausen criterion)
For the oscillator to oscillate and remain stable, two conditions must be fulfilled simultaneously:
Amplitude condition: |R_neg| > ESR of the quartz crystal (typically factor 5× recommended)
Phase condition: The total phase rotation in the feedback path is 360°
The negative input resistance R_neg of a typical CMOS inverter at 40 MHz is in the range from -200 Ω to -1000 Ω. With an ESR of 35 Ω, the amplitude condition is in principle easy to fulfil - without R_S, however, it is uncontrolled and associated with high drive power.
Note: The gain margin should be at least a factor of 5 above the minimum value in order to cover fluctuations in temperature, supply voltage and component tolerance. For automotive applications, the required transient response safety factor is >10.
4 The serial resistor R_S
4.1 Function and significance
R_S is - contrary to the first impression - not an optional component slot, but a function-critical component with several tasks:
Function of R_S
Explanation
Drive power limitation
Prevents excessive current flow through the crystal; protects against mechanical overload and thus extends the service life of the oscillating crystal
Amplitude stabilisation
Reduces effective negative resistance to a controlled level
Low-pass filtering
Forms an RC low-pass filter with C1/C2 that dampens harmonics and parasitic resonances
Decoupling
Isolates the low-impedance CMOS output from the capacitive load; improves phase reserve
4.2 Dimensioning recommendation
For a 40 MHz crystal with ESR = 35 Ω and C_L = 12 pF, the following guide values apply:
Scenario
R_S value
Remark
Conservative - safe transient response
220 Ω
Maximum gain reserve; moderate harmonic attenuation
Balanced - recommendation
330 Ω
Good compromise between starting behaviour and EMC
EMC-optimised
470 Ω
Strongest harmonic suppression; slightly longer settling time
Note: Recommendation: With R_S = 330 Ω to 470 Ω, you are always on the safe side in practice for the frequency range 10-50 MHz. For proven EMC problems, 470 Ω is the first starting point.
4.3 Limit consideration
An excessively large R_S can violate the oscillation condition if the negative resistance of the inverter is low. Rule of thumb for the upper limit:
R_S_max ≈ |R_neg| / 5 - ESR
For R_neg = -300 Ω (conservative assumption for 40 MHz): R_S_max ≈ 300/5 - 35 = 25 Ω ... This shows: The actual negative resistance must be known or derived from the data sheet of the IC used. If in doubt, always carry out measurements at Tmin and Vcc_min.
Attention: If R_neg is unknown: R_S = 330 Ω with verification by commissioning measurement (oscilloscope, spectrum analyser) under extreme conditions (-40 °C, Vcc_min).
5 Load capacities C1 and C2
5.1 Calculating the effective load capacitance
The effective load capacitance C_L_eff seen by the quartz results from the series connection of C1 and C2 plus the parasitic stray capacitance C_stray of the conductor track and the IC pad:
C_L_eff = (C1 × C2) / (C1 + C2) + C_stray
C_stray is in the range of 2-5 pF on a typical PCB. C_stray = 3 pF is used as a realistic assumption for the design.
5.2 Comparison: 12 pF vs. 18 pF per capacitor
Parameters
C1 = C2 = 12 pF
C1 = C2 = 18 pF
C_L_eff (C_stray = 3 pF)
6 + 3 = 9 pF
9 + 3 = 12 pF ✓
Deviation from Spec. (12 pF)
-3 pF (-25 %)
0 pF (target value)
Frequency error
positive (too high)
nominally correct
Low-pass cut-off frequency (R_S=330Ω)
approx. 40 MHz
approx. 27 MHz
Harmonic attenuation @360 MHz
approx. 19 dB
approx. 22 dB
Sensitivity to C_stray
high (33 %)
low (17 %)
5.3 Recommendation
C1 + C2 = 18 pF is the optimum choice for a crystal with a load capacitance of C_L = 12 pF on a standard PCB. This choice
meets the specified load capacitance at C_stray ≈ 3 pF almost exactly
completely reduces the positive frequency error compared to C1=C2=12 pF
improves the harmonic suppression by approx. 3 dB
is less sensitive to stray capacitance variations in the layout
Note: If C_stray cannot be reliably estimated on the PCB, it is recommended to use 22 pF with the option of reducing to 18 pF or 15 pF (NP placement). This allows iterative frequency optimisation without PCB redesign.
6 EMC optimisation - CISPR 25
6.1 Cause of harmonic emission at 360 MHz
Exceeding the limit value at 360 MHz in the context of CISPR 25 measurements is a known phenomenon with 40 MHz Pierce oscillators. 360 MHz corresponds to the 9th harmonic of the fundamental (9 × 40 MHz = 360 MHz).
The main cause lies in the steep edge steepness of the CMOS inverter: switching times in the 0.5-2 ns range generate a rich harmonic spectrum that reaches the conductors unattenuated without sufficient low-pass filtering.
6.2 Chain of effects and attenuation calculation
The RC low-pass filter, which forms R_S together with C1 (or C2), provides the following attenuation at 360 MHz:
Attenuation [dB] = 20 × log₁₀(f / f_c) with f_c = 1 / (2π × R_S × C)
Combination R_S / C
Cut-off frequency f_c
Attenuation @360 MHz
330 Ω / 12 pF
40.3 MHz
~19 dB
330 Ω / 18 pF
26.8 MHz
~22 dB
470 Ω / 18 pF
18.8 MHz
~25 dB
470 Ω / 22 pF
15.4 MHz
~27 dB
6.3 Package of measures
The following measures are recommended in order of priority:
Measure
Description / Expected effect
1. increase R_S to 470 Ω
Most direct measure; reduces edge steepness and shifts low-pass cut-off frequency
2. increase C1/C2 to 18 pF
Improves low-pass effect, simultaneously corrects the operating frequency of the quartz crystal
3. decoupling V_CC oscillator stage
Series ferrite (e.g. 600 Ω @100 MHz) on V_CC prevents radiation via supply network
4. optimise PCB layout
Place feedback network (R_S, C1, C2) close to the IC; connect crystal to GND (usually pads #2 and #4 on 4pad housings)
5. housing / shielding
For very strict CISPR-25 classes: metallic shielding cap over oscillator stage
Attention: None of the measures should be considered in isolation. The combination of R_S = 470 Ω and C1/C2 = 18 pF is the first recommended step; it addresses the cause (low-pass filtering) and not just the symptom.
7 Dimensioning checklist
This checklist summarises all the steps for correct Pierce oscillator wiring:
Step
Action / checkpoint
✅ Quartz parameters
Take ESR, C_L, nominal frequency from data sheet
✅ Calculate C_L_eff
Formula: C_L_eff = C1×C2/(C1+C2) + C_stray; estimate or measure C_stray
1 MΩ parallel to the quartz branch; DC operating point of the inverter
✅ Select R_S
330 Ω (standard) or 470 Ω (EMC-optimised); never < 100 Ω at f > 10 MHz
Gain reserve ✅ Gain reserve
If R_neg is known: check |R_neg| > 5 × (ESR + R_S)
✅ Start-up test
Commissioning at Vcc_min and T_min; verify start-up with oscilloscope
✅ Frequency accuracy
Measure frequency with reference measuring device; adjust C1/C2 if necessary
EMC pre-test
Spectrum analyser: check harmonics up to 1 GHz; observe CISPR 25 class
✅ Layout review
Minimise loop area of crystal feedback path; no line routing underneath
8 Reference circuit: 40 MHz quartz crystal
The following table shows the fully dimensioned reference circuit for a 40 MHz quartz with C_L = 12 pF and ESR = 35 Ω:
Component
Component Value
Remark
Quartz
40 MHz, C_L=12 pF, ESR=35 Ω
Example type; parameterisation applies accordingly
R_P
1 MΩ
Parallel; DC operating point; 5 % tolerance sufficient
R_S
470 Ω
Serial; EMC-optimised; 1 % or 5 % tolerance
C1
18 pF
To GND; COG/NP0; 5 % tolerance
C2
18 pF
According to GND; COG/NP0; 5 % tolerance
C_stray (PCB)
~3 pF
Assumption; layout-dependent; adjust if necessary
C_L_eff (calculated)
~12 pF
= 18×18/(18+18) + 3 = 9 + 3 ≈ 12 pF ✓
Ferrite V_CC (optional)
600 Ω @100 MHz
Only for strict EMC requirements
9 Common errors and remedial measures
Error pattern
Cause
Remedy
Quartz does not oscillate
R_S too high; R_neg of the IC too low; C1/C2 too high
Reduce R_S; change IC; reduce C1/C2
Frequency too high
C_L_eff < spec. C_L (C1/C2 too small)
Increase C1/C2 (e.g. 12→18 pF)
Frequency too low
C_L_eff > spec. C_L (C1/C2 too high)
Reduce C1/C2
Harmonics / EMC error
R_S missing or too small; C1/C2 too small
R_S = 470 Ω, C1/C2 = 18 pF, ferrite V_CC
Resonance dependent on temperature
Low gain reserve
Increase gain reserve; reduce R_S
Quartz ageing / failures
Drive level too high (no R_S)
R_S must be fitted; check drive power
10 Further standards and literature
IEC 60122-1: Quartz resonators - Definitions and methods of measurement
CISPR 25: Limits and methods of measurement for radio interference suppression in vehicles
Colpitts, E. H. (1918): Original patent of the Colpitts/Pierce oscillator
Marvin, A. / Dawson, J.: Crystal Oscillator Design and Temperature Compensation, Van Nostrand Reinhold
Disclaimer: This application note is for guidance only. All dimensions must be verified by measuring the end product. PETERMANN-TECHNIK GmbH cannot be held liable for any damage resulting from the use of this information.
