Practical guide for electronics developers

In order for a crystal oscillator (oscillating crystal in the oscillator stage of an IC) to oscillate stably, precisely and reliably, the crystal used must be optimally matched to the requirements of the respective IC.

The load capacitances, transient conditions, drive level (quartz current) and layout factors on the PCB are decisive factors here.

This article explains in a compact and practical way how to correctly tune a crystal clock generator and which errors occur particularly frequently in practice.

A. Why crystals and ICs need to be tuned

Crystals are frequency-determining components whose accuracy is highly dependent on their electrical environment. Microcontroller manufacturers typically specify

required load capacitance (CL)
permissible drive level
Required start time
Oscillator topology and internal amplification

Only if these parameters match the crystal will the oscillator operate within its tolerances and fulfil timing requirements such as wireless, USB, CAN, Ethernet, UART baud rates, etc.

B. The role of load capacity (CL)

The load capacitance defines the operating point of the oscillation frequency. Each crystal is trimmed to a specific CL (e.g. 8 pF, 12 pF, 16 pF).

The effective load capacitance results from:

Typical parasitic capacitances:

IC pin: 1-3 pF
Traces: 0.5-2 pF
Solder pads: 0.5-1 pF

If CL is selected too small: The frequency increases → Timing error possible.
If CL is selected too large: The frequency decreases and the oscillator can start poorly.

C. Dimensioning of external capacities

The external capacitances C1 and C2 are selected so that:

Dimensioning of external capacities Formula

Typical guide values:

Quartz CL	C1/C2 starting value
6 pF	12-15 pF
8 pF	15-18 pF
12.5 pF	18-20 pF

A precise adjustment is often made via measurements or manufacturer recommendations.

As a calculation example:

Question: "What external capacitances do I need to connect to a CL 12pF crystal?"

Based on the above formula, the following is calculated:

¹⁸² divided by 36 plus 2pF = 18 pF (CX1 and CX2 should each be 18pF to GND)

The in-circuit measurements of our oscillating crystals in customer circuits showed a stray capacitance(C parasitic) of 2pF as a very reliable average parameter.

However, there are also IC manufacturers who describe a capacitive load of XIN/XOUT of up to 7pF in their data sheets. It is therefore important to read the data sheet again before calculating the circuit capacitances for the crystal oscillator to see what capacitive load may be specified for XIN/XOUT.

If the crystal oscillator is to be used in an application with higher long-term accuracy, for example in wireless applications for the ISM band, we recommend the use of 1% tolerated circuit capacitances.

D. Drive level and power loss

The drive level (typically 1-200 µW) indicates how much power the quartz can tolerate permanently.

Too high a drive level leads to

Increased ageing and drift
Increased frequency stability
Increase in the series resonance resistance
Faulty failures due to cracks in the quartz platelet

Too low a drive level causes

unreliable starting
Increased jitter values

Oscillator ICs usually specify the typical and maximum drive level; a measurement is recommended.

As the resonator designs for the SMD crystals we supply are developed in-house, we can also supply MHz oscillator crystals with high drive level stability in small ceramic housings. The low ESR mini crystal of the SMD03025/4 series up to 500 µW and the ultra-miniature MHz crystal of the SMD02016/4 series up to 400 µW.

E. Start-up time (start time)

The start time depends on:

Gain of the oscillator in the IC
Quartz ESR (Equivalent Series Resistance)
Load capacitance of the quartz oscillator
Values of the external circuit capacitances
Temperature and supply voltage

Excessive CL values often significantly extend the start-up time → problematic for low-power MCUs with sleep cycles.

F. ESR - an underestimated parameter

The ESR influences

Transient behaviour and transient stability
Energy consumption
Transient behaviour at low quartz currents

Many ICs specify a maximum ESR (e.g. 70 Ω). If the crystal is above this, the oscillator cannot start safely.

F.1: Why oscillator stages have a negative input resistance

In capacitive Pierce oscillators - by far the most commonly used topology in microcontrollers - the internal inverter of the IC operates in an analogue operating range in which it behaves like an amplifier with negative impedance. This negative input resistance (-Rneg) is intentional and ensures that:

the crystal receives energy from the oscillator circuit,
losses in the crystal (ESR) are compensated,
the oscillation grows independently and becomes stable.

Simplified, the starting condition is

This means: The value of the negative input resistance must be greater than the series resistance (ESR) of the crystal.

Only then will there be a net amplification that leads to oscillation.

F.2: Influence on the transient response safety

If the amount of the negative input resistance is too small (i.e. -Rneg is too weak), the following happens:

The crystal receives too little energy → slow or no oscillation
The oscillation only starts at a higher supply voltage or temperature
The start-up in low-power operating modes becomes unreliable

Typical cause:
For efficiency reasons, some modern MCUs have weak oscillator amplifiers, which means that -Rneg is smaller than in older IC generations. At the same time, many designs work with small load capacitances or long traces, which increases parasitic losses.

F.3: Why crystals with low ESR are particularly important

The ESR of the quartz crystal defines its internal losses. A low ESR means:

Lower losses
Lower counteramplification required
High transient response reliability even with weak oscillator stages
Lower start time
More stable oscillation over temperature

Practical recommendation:
- Use crystals whose ESR is well below the maximum value specified by the IC.
- If a microcontroller specifies e.g. max. 70 Ω ESR, a crystal with 30-50 Ω ESR is ideal. This leaves a sufficient safety margin against a possibly low negative input resistance of the oscillator.

F.4: Conclusion on the interaction of -Rneg and quartz ESR

The transient response reliability essentially depends on:

the internal oscillator provides sufficient negative input resistance,
the quartz has a sufficiently low ESR,
the load capacitances are correctly dimensioned.

Only if the ratio of -Rneg to ESR is correct will the quartz start quickly, reliably and over the entire temperature and voltage range.

G. Layout recommendations

The following applies to crystals:

Place the crystal + capacitors as close as possible to the IC
Short, symmetrical traces
No signals or ground planes directly under the crystal - reduces parasitic capacitance
Dedicated GND island for the capacitors
If possible, connect the crystal to GND (with our SMD oscillating crystals in ceramic housing, pads #2 and #4 can be connected to GND. But please connect the crystal to GND immediately and do not change it for frequency tuning in the circuit.

These measures improve EMC, jitter and starting behaviour.

H. Common mistakes in practice

Incorrect CL selection → Frequency error
Crystal with too high ESR → Does not start reliably
Drive level exceeded → crystal drifts strongly
Poor layout → Unstable oscillation
Parasitic capacitances incorrectly taken into account

I. Conclusion

The optimum matching of a crystal to an IC is crucial for the reliability of the oscillator and the long-term operation of the crystal resonator in the circuit (drive level matching). With the correct load capacitance, correct drive level, suitable ESR and a good layout, developers can ensure stable frequency references.

Technical explanation of the oscillator diagrams

Overview

The diagrams shown describe the physical and electrical mechanisms that determine the starting and operating behaviour of a quartz-stabilised Pierce oscillator. The focus is in particular on

the negative input resistance of the oscillator stage,
the loss model of the quartz crystal (ESR),
the starting condition according to the Barkhausen criterion,
the temporal structure of the drive level,
parasitic capacitances and
layout-related influencing factors.

These parameters are decisive for the swing-on safety reserve, swing-on time, frequency accuracy, jitter and long-term stability.

1. pierce oscillator and negative input resistor

(top left illustration)

This diagram shows the classic Pierce oscillator circuit as integrated in most microcontrollers and ASICs. The Pierce oscillator is based on an inverting amplifier that is forced into linear operation by feedback via the quartz crystal. At this operating point, the input stage can be described by a small-signal equivalent model with a negative real part of the impedance.

Mathematically, the following applies:

This negative resistor represents an active energy source that compensates for the losses occurring in the quartz.

Important properties of -Rneg:

dependent on supply voltage, temperature and process variation
strongly influenced by internal bias networks
deliberately reduced in low-power designs

Technical significance:

The internal inverter of the IC operates in the linear range and behaves like a negative resistor (-Rₙₑg).
This negative input resistance compensates for the losses of the quartz (its ESR).
Only if sufficient negative impedance is present, the oscillation can grow.

Core statement:
The oscillator stage supplies energy - the crystal determines the frequency.

2. load capacity model of the quartz crystal

(upper centre illustration)

This illustration shows the quartz crystal with the two external circuit capacitors C₁ and C₂.

The quartz can be described electrically by a series RLC element (_R1, _L1,_C1) with a parallel package capacitance _C0. The ESR (Equivalent Series Resistance) represents the mechanical losses of the oscillation system.

The external wiring with C₁ and C₂ defines the effective load capacitance:

Deviations from the specified CL lead to

Systematic frequency offset
Changed phase angle in the control loop
reduced negative resistance reserve

Technical significance:

The effective load capacitance determines the actual operating frequency of the quartz.
C₁ and C₂ act in series, with additional parasitic capacitances.
The quartz is always specified for a defined load capacitance (e.g. 8 pF or 12 pF).

Key message:
Incorrect load capacitance leads to frequency deviations and poorer transient behaviour.

3. startup condition and negative resistance reserve (Start-up condition: |Rₙₑg| > Rₑₛᵣ)

(upper right illustration)

The necessary start condition results from the Barkhausen criterion:

Loop gain ≥ 1
Phase shift = 0° (or 360°)

In the impedance model this is reduced to:

A safety reserve is recommended for robust designs:

The following is required in automotive applications:

Consequences of insufficient reserve:

Extended, unstable start time
Temperature-dependent non-swinging
Start problems at low supply voltage

This simple inequality describes the fundamental start-up condition.

<p

<p>Technical meaning:

The value of the negative input resistance must be greater than the ESR of the crystal.
If this condition is not met, the crystal will not oscillate or will only oscillate unreliably.
Modern low-power MCUs often have a smaller -Rₙₑg than older designs.

Core statement:
Crystals with low ESR are crucial for safe oscillation in the oscillator stage.

>All oscillator crystals supplied by us feature the exclusive LRT technology (Low ESR Resonator Technology). Our innovative LRT resonant crystals have very low ESR values by design (at +25°C and over the corresponding specified temperature range), so that they offer the circuit designer a great deal of transient response reserve and can always be used very quickly and very safely in the circuit under all circumstances.

4. temporal structure of the drive level

(bottom left diagram)

This curve shows the build-up of the oscillation amplitude over time after switching on.

After switching on, the oscillator starts in the noise range. The oscillation amplitude increases exponentially in accordance with:

whereby the time constant τ is determined by the difference between negative gain and losses.

Drive level limits:

Upper limit due to mechanical load capacity of the quartz
Lower limit due to energy supply required for stabilisation

A drive level that is too high accelerates ageing and drift, one that is too low worsens jitter and starting behaviour

.

Technical significance:

In the beginning, the oscillation is very small and grows exponentially.
The steady-state drive level results from the balance between gain and losses.
Too high a drive level can damage the crystal, too low a drive level makes starting more difficult.

Core statement:
A correctly dimensioned oscillator starts quickly and operates the crystal within the permissible power range.

5 Parasitic capacities and their effects

(lower centre illustration)

Parasitic capacitances are caused by

IC pins (typically 1 - 3 pF)
Conductor tracks (≈ 0.5 - 2 pF)
Solder pads and housing

These capacitances:

increase the effective load capacitance
reduce the amount of -Rneg
shift the optimum operating point

Designs with a low specified CL are particularly critical, as parasitic effects have a strong percentage effect there. In battery-powered applications, SMD crystals with low load capacitances are usually specified by the corresponding IC manufacturers. MHz crystal typ. 8 pF. 32.768 kHz crystal up to 4 pF. In such applications, it is advisable to select a tolerance of 1% max. for the external circuit capacitances C₁ and C₂. This can greatly reduce parasitic influences on the operating frequency of the quartz.

Technical significance:

Parasitic capacitances increase the effective load capacitance unintentionally.
They influence the crystal frequency, transient response time and reliability, as well as the negative resistance reserve.
They are particularly critical for low CL crystals (< 10 pF).

Key message:
Parasitic capacitances must always be taken into account when dimensioning load capacitors/external circuit capacitances.

6. layout influence on oscillator stability

(bottom right illustration)

This schematic illustration shows recommended layout principles. The PCB layout has a greater influence on the crystal behaviour in the circuit than is often assumed.

Technical significance:

Connect the crystal and load capacitors very close to the IC
Short, symmetrical traces
No signals or ground planes under the crystal
Dedicated, clean ground routing

Key message:
A poor layout can render even an optimally selected crystal unusable.

7. summary:

The figure illustrates that the function of a crystal oscillator depends not only on the crystal itself, but also on the interaction between the IC oscillator, ESR, load capacitance, parasitic effects and layout.

The following conditions must be met for a robust oscillator design:

Quartz withlow ESRselect
to ensure sufficient negative resistance reserve
Calculate load capacities realistically
Consistently optimise the layout

Key message:

The quartz should not only fulfil the IC specification, but should be significantly lower in order to reliably compensate for process, temperature and ageing influences.

Or simply give our specialists a call. You will receive full design-in support from us. Your success is our goal!

Give us a call!Contact us by e-mail!Call me back!

Optimally tune crystals to ICs

Practical guide for electronics developers

A. Why crystals and ICs need to be tuned

B. The role of load capacity (CL)

C. Dimensioning of external capacities

D. Drive level and power loss

E. Start-up time (start time)

F. ESR - an underestimated parameter

G. Layout recommendations

H. Common mistakes in practice

I. Conclusion

Technical explanation of the oscillator diagrams

Overview

1. pierce oscillator and negative input resistor

2. load capacity model of the quartz crystal

3. startup condition and negative resistance reserve (Start-up condition: |Rₙₑg| > Rₑₛᵣ)

4. temporal structure of the drive level

5 Parasitic capacities and their effects

6. layout influence on oscillator stability

7. summary:

Telephone contact

Write to us