Optimally tune crystals to ICs

In order for a crystal oscillator (oscillating crystal in the oscillator stage of an IC) to oscillate stably, precisely and reliably, the crystal used must be optimally matched to the requirements of the respective IC.

The load capacitances, transient conditions, drive level (quartz current) and layout factors on the PCB are decisive factors here.

This article explains in a compact and practical way how to correctly tune a crystal clock generator and which errors occur particularly frequently in practice.

Crystals are frequency-determining components whose accuracy is highly dependent on their electrical environment. Microcontroller manufacturers typically specify

• required load capacitance (CL)
• permissible drive level
• Required start time
• Oscillator topology and internal amplification

Only if these parameters match the crystal will the oscillator operate within its tolerances and fulfil timing requirements such as wireless, USB, CAN, Ethernet, UART baud rates, etc.

The load capacitance defines the operating point of the oscillation frequency. Each crystal is trimmed to a specific CL (e.g. 8 pF, 12 pF, 16 pF).

The effective load capacitance results from:

The external capacitances C1 and C2 are selected so that:

The drive level (typically 1-200 µW) indicates how much power the quartz can tolerate permanently.

Too high a drive level leads to

• Increased ageing and drift
• Increased frequency stability
• Increase in the series resonance resistance
• Faulty failures due to cracks in the quartz platelet

Too low a drive level causes

• unreliable starting
• Increased jitter values

Oscillator ICs usually specify the typical and maximum drive level; a measurement is recommended.

As the resonator designs for the SMD crystals we supply are developed in-house, we can also supply MHz oscillator crystals with high drive level stability in small ceramic housings. The low ESR mini quartz of the series SMD03025/4 up to 500 µW, or the ultra-miniature MHz quartz of the series SMD02016/4 up to 400 µW.

The start time depends on:

• Gain of the oscillator in the IC
• Quartz ESR (Equivalent Series Resistance)
• Load capacitance of the quartz oscillator
• Values of the external circuit capacitances
• Temperature and supply voltage

Excessive CL values often significantly extend the start time → problematic for low-power MCUs with sleep cycles.

The ESR influences

• Transient behaviour and transient stability
• Energy consumption
• Transient behaviour at low quartz currents

Many ICs specify a maximum ESR (e.g. 70 Ω). If the quartz is above this, the oscillator cannot start safely.

The following applies to crystals:

• Place the crystal + capacitors as close as possible to the IC
• Short, symmetrical traces
• No signals or ground planes directly under the crystal - reduces parasitic capacitance
• Dedicated GND island for the capacitors
• If possible, connect the crystal to GND (with our SMD oscillating crystals in ceramic housing, pads #2 and #4 can be connected to GND. But please connect the crystal to GND immediately and do not change it for frequency tuning in the circuit.

These measures improve EMC, jitter and starting behaviour.

• Incorrect CL selection → Frequency error
• Crystal with too high ESR → Does not start reliably
• Drive level exceeded → crystal drifts strongly
• Poor layout → Unstable oscillation
• Parasitic capacitances incorrectly taken into account

The optimum matching of a crystal to an IC is crucial for the reliability of the oscillator and the long-term operation of the crystal resonator in the circuit (drive level matching). With the correct load capacitance, correct drive level, suitable ESR and a good layout, developers can ensure stable frequency references.

Overview

The diagrams shown describe the physical and electrical mechanisms that determine the starting and operating behaviour of a quartz-stabilised Pierce oscillator. The focus is in particular on

• the negative input resistance of the oscillator stage,
• the loss model of the quartz crystal (ESR),
• the starting condition according to the Barkhausen criterion,
• the temporal structure of the drive level,
• parasitic capacitances and
• layout-related influencing factors.

These parameters are decisive for the swing-on safety reserve, swing-on time, frequency accuracy, jitter and long-term stability.

(top left illustration)

This diagram shows the classic Pierce oscillator circuit as integrated in most microcontrollers and ASICs. The Pierce oscillator is based on an inverting amplifier that is forced into linear operation by feedback via the quartz crystal. At this operating point, the input stage can be described by a small-signal equivalent model with a negative real part of the impedance.

Mathematically, the following applies:

(upper centre illustration)

This illustration shows the quartz crystal with the two external circuit capacitors C₁ and C₂.

The quartz can be described electrically by a series RLC element (_R1, _L1,_C1) with a parallel package capacitance _C0. The ESR (Equivalent Series Resistance) represents the mechanical losses of the oscillation system.

The external wiring with C₁ and C₂ defines the effective load capacitance:

(upper right illustration)

The necessary start condition results from the Barkhausen criterion:

• Loop gain ≥ 1
• Phase shift = 0° (or 360°)

(bottom left diagram)

This curve shows the build-up of the oscillation amplitude over time after switching on.

After switching on, the oscillator starts in the noise range. The oscillation amplitude increases exponentially in accordance with:

(lower centre illustration)

Parasitic capacitances are caused by

• IC pins (typically 1 - 3 pF)
• Conductor tracks (≈ 0.5 - 2 pF)
• Solder pads and housing

These capacitances:

• increase the effective load capacitance
• reduce the amount of -Rneg
• shift the optimum operating point

Designs with a low specified CL are particularly critical, as parasitic effects have a strong percentage effect there. In battery-powered applications, SMD crystals with low load capacitances are usually specified by the corresponding IC manufacturers. MHz crystal typ. 8 pF. 32.768 kHz crystal up to 4 pF. In such applications, it is advisable to select a tolerance of 1% max. for the external circuit capacitances C₁ and C₂. This can greatly reduce parasitic influences on the operating frequency of the quartz.

Technical significance:

• Parasitic capacitances increase the effective load capacitance unintentionally.
• They influence the crystal frequency, transient response time and reliability, as well as the negative resistance reserve.
• They are particularly critical for low CL crystals (< 10 pF).

Key message:
Parasitic capacitances must always be taken into account when dimensioning the load capacitors/external circuit capacitances.

(bottom right illustration)

This schematic illustration shows recommended layout principles. The PCB layout has a greater influence on the crystal behaviour in the circuit than is often assumed.

Technical significance:

• Connect the crystal and load capacitors very close to the IC
• Short, symmetrical traces
• No signals or ground planes under the crystal
• Dedicated, clean ground routing

Key message:
A poor layout can render even an optimally selected crystal unusable.

The figure illustrates that the function of a crystal oscillator depends not only on the crystal itself, but also on the interaction between the IC oscillator, ESR, load capacitance, parasitic effects and layout.

The following conditions must be met for a robust oscillator design:

• Quartz withlow ESRselect
• to ensure sufficient negative resistance reserve
• Calculate load capacities realistically
• Consistently optimise the layout
  

Key message:

The quartz should not only fulfil the IC specification, but should be significantly lower in order to reliably compensate for process, temperature and ageing influences.

Or simply give our specialists a call. You will receive full design-in support from us. Your success is our goal!