Practical measurement methods for the post "Optimising quartz crystals for ICs" - sections B and 5
To the encyclopaedia article : Matching crystals optimally to ICs
What it's all about
Parasitic capacitances (Cpar) between XIN/XOUT and ground are unavoidable. They are made up of IC pin capacitance, trace capacitance, pad capacitance and package capacitance. Typical values are between 1 pF and 3 pF per side, in unfavourable layouts or with IC pin capacitances up to 7 pF even significantly higher.
These capacitances increase the effective load capacitance, reduce the amount of -Rneg and shift the operating point of the oscillator. Designs with a low specified CL (MHz quartz ≤ 10 pF, 32.768 kHz quartz ≤ 6 pF) are particularly critical - parasitic capacitances have a strong percentage effect here.
This post describes two practical methods for the quantitative determination of Cpar.
Why Cpar should be measured
From data sheet rules of thumb, Cpar = 2 pF is often calculated. However, the real dispersion across different layouts is considerable:
| Layout type | Cpar typical | Effect on CL_eff |
|---|---|---|
| 4-layer PCB, short leads, quartz directly at the IC | 1.0 - 1.5 pF | minimum |
| 4-layer PCB, standard layout with 5 mm leads | 2.0 - 2.5 pF | normal, to be considered in invoice |
| 2-layer PCB, long leads (> 10 mm) | 3.0 - 4.5 pF | significant, CL frequency error > 10 ppm possible |
| IC with increased pin capacitance (CIN up to 7 pF) | 7 - 9 pF | dominates the capacitance balance |
| GND area directly under quartz pads | 4 - 7 pF | Layout error, must be corrected |
Method A: Frequency variation method (recommended)
Two frequency measurements with different C1/C2 configurations provide Cpar indirectly via the frequency change. This method is the most reliable because it measures Cpar under real operating conditions (including IC pin capacitance at nominal voltage and operating temperature).
Equipment
- Frequency counter ≥ 0.1 ppm resolution with GPS or OCXO reference
- Two sets of precise C0G/NP0 capacitors (±1 %), e.g. C_A = 10 pF and C_B = 22 pF
- FET probe with ≤ 1 pF input capacitance (at XOUT)
- Known pull sensitivity S [ppm/pF] of the crystal used (from data sheet, measurement or measurement protocols enclosed with our sample deliveries)
Measurement procedure
- Placement A: C1 = C2 = C_A. After 60 s transient response, measure frequency f_A, Δf_A = (f_A - f_nenn)/f_nenn in ppm.
- Fitting B: C1 = C2 = C_B. Measure frequency f_B, calculate Δf_B.
- Both fittings refer to the same pull sensitivity. Cpar follows from the system of equations.
Calculation
With CL_eff_A = C_A/2 + Cpar and CL_eff_B = C_B/2 + Cpar and Δf = S - (CL_eff - CL_spec), the following results:
Cpar = CL_spec + (Δf_A / S) - C_A / 2
For checking purposes, Cpar can be calculated analogue from assembly B - both results should match within ±0.3 pF. If they deviate more, this indicates incorrect pull sensitivity, incorrectly recognised CL_spec or a strong drive level influence.</p
<h3>Example calculation
Crystal: 26 MHz, CL_spec = 8 pF, S = -20 ppm/pF.
| Population | C1 = C2 | Δf measured | CL_eff from Δf |
|---|---|---|---|
| A | 10 pF | +1.60 ppm | 7.92 pF |
| B | 22 pF | -3.20 ppm | 8.16 pF |
Cpar_A = 7.92 pF - 10/2 = 2.92 pF
Cpar_B = 8.16 pF - 22/2 = -2.84 pF
The values do not match (different sign). Reason: With configuration B, CL_eff is greater than CL_spec, therefore negative deviation. For correct interpretation, use the formulation with the correct sign:
CL_eff_A = 5 + Cpar = 7.92 → Cpar = 2.92 pF
CL_eff_B = 11 + Cpar = 8.16 ... ?
The second equation shows an inconsistency: 11 + Cpar cannot be 8.16. This indicates that at C_B = 22 pF the crystal is operated above its CL_spec and the linear approximation loses its validity. In this case, select two assemblies with a smaller spread (e.g. C_A = 12 pF, C_B = 18 pF) or carry out an exact crystal equivalent circuit diagram calculation.
Note: The frequency method works best if both placements result in CL_eff values around CL_spec. Cpar ≈ 2.9 pF from assembly A is the meaningful result here.
Method B: LCR measurement when switched off
Supplementary method that does not require oscillation. It is suitable for prototype characterisation and for comparisons between layout variants.</p
<h3>Measurement setup
- Precision LCR meter with 1 MHz signal (e.g. Keysight E4980AL, HP 4284A)
- Measurement signal ≤ 100 mV to avoid stressing the IC input diodes
- Circuit completely de-energised (VCC = 0 V, no battery)
Implementation
- Remove the quartz crystal from the socket (for SMD: desolder or do not assemble).
- Without C1 and C2 (not assembled): Measure capacitance XIN → GND and XOUT → GND. This gives an estimate of the pure pin and track capacitance to ground.
- With C1 and C2 fitted: Measure capacitance XIN → GND and XOUT → GND again. The difference to the measurement without capacitors must correspond to the C1/C2 values plus a small stray capacitance (< 0.5 pF).
- Cpar ≈ measured value without C1/C2.
Limit of the LCR method The IC pin capacitance is voltage-dependent and typically changes by 0.5 - 1.5 pF between switched off and switched on states. The LCR measurement therefore only provides a lower limit of the operating Cpar. For absolute precision, use the frequency method (method A). |
Layout influences on Cpar
| Layout measure | Effect on Cpar | Recommendation |
|---|---|---|
| shorten trace by 5 mm | -0.3 to -0.5 pF | always |
| Remove GND area under quartz pads | -1.0 to -2.5 pF | Always, whether for MHz or kHz quartz crystals = no ground directly under the quartz crystal |
| Place quartz pads #2 and #4 on GND (4-pad ceramic) | +0 pF, but EMC improvement | recommended, but specify once before fine frequency adjustment |
| Via instead of trace to GND | minimal | only if routing forces it |
| Populate the crystal from the underside of the PCB | +0.5 - 1.0 pF | avoid, if possible |
| additional signalling track at < 1 mm distance | +0.3 to +1.0 pF | avoid at all costs |
Recommendation for low-CL designs
In battery-powered applications, IC manufacturers often specify crystals with very low load capacitances (MHz quartz typically 8 pF, 32.768 kHz quartz down to 3 - 4 pF). In such designs:
- Use 1 %-tolerated C0G/NP0 capacitors for C1 and C2
- Verify Cpar by frequency measurement once per layout
- Maximum 3 mm trace between IC pin and crystal pad
- No signal lines under or directly next to the crystal
- Dedicated GND island for the circuit capacitors
TS (Tuning Sensivity) in ppm/pF: The IC manufacturers are increasingly recommending the use of oscillating crystals with low load capacitances (MHz = <6pF, 32.768 kHz = 4pF). Less XIN/XOUT load reduces the power consumption of the IC and thus extends the battery life and increases the transient response. On the frequency side, however, this poses a major problem for the development engineer. This is because the lower the load capacitance of the quartz, the greater the draw sensitivity in ppm/pF (physical legislation). This is irrelevant for a normal controller circuit, but this value is essential for a radio application. We therefore recommend using a maximum tolerance of 1% for C1 and C2 in radio applications so that as little capacitive frequency offset (shift of the operating frequency) as possible is generated from the side. In addition, the capacitive tolerance on XIN/XOUT, which can be up to 25%, should not be neglected. |
Limit of the LCR method
The IC pin capacitance is voltage-dependent and typically changes by 0.5 - 1.5 pF between a switched-off and switched-on state. The LCR measurement therefore only provides a lower limit of the operating Cpar.</p
<h2>For absolute precision, use the frequency method (method A)</h2
<h2>Further information
The effect of parasitic capacitances on the operating point, transient response and frequency accuracy is described in the practical guide "Tuning crystals optimally to ICs" (sections B and 5). This post shows how to quantitatively determine Cpar on your board and reduce it through targeted layout measures.
You have questions about implementation
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