Practical measurement methods for the post "Optimising quartz crystals for ICs" - Sections G and 6
To the encyclopaedia article : Matching crystals optimally to ICs
What it's all about
A poor PCB layout can make even an optimally selected crystal unusable. At the same time, the layout affects several properties simultaneously - parasitic capacitance, |-Rneg| reserve, jitter, EMC behaviour and transient response. This post describes a structured test that is used to finally validate a crystal layout on the finished board.
Layout checklist (design check)
Before the measurement, the layout is checked against the established design rules:
| Rule | Criterion | Test |
|---|---|---|
| Position | Quartz + C1, C2 directly at IC | Distance < 5 mm to XIN/XOUT |
| Symmetry | C1/C2 lines of equal length | ±1 mm difference |
| Isolation | No signals under or next to quartz | Wedge ring around quartz ≥ 2 mm |
| ground plane | No GND plane directly under quartz | recess on all layers |
| GND island | Dedicated GND area for C1, C2 | Dedicated connection to main GND |
| Quartz housing | Pads #2/#4 on GND (4-pad ceramic) | direct connection, < 1 mm |
| protection | No change of layers under quartz | Vias outside |
| EMV | Distance to clock lines | ≥ 5 mm to clock lines |
| Humidity/creepage paths | Conformal coating distance | Consider harsh environment |
Measurement-based layout validation
The following measurements on the finished board reveal the typical layout weaknesses:
Validation 1: Jitter measurement at the oscillator output
- Oscilloscope ≥ 1 GHz with jitter analysis function (period jitter, cycle-to-cycle jitter)
- Measurement point: output of the clock signal driven by the crystal oscillator (PLL output, SYSCLK pin, UART baud rate pin)
- Expectation: period jitter < 30 ps RMS for standard applications; < 10 ps RMS for USB, Ethernet, HDMI
Increased jitter (< 50 ps RMS) indicates coupling from neighbouring signals, improper grounding or too low a drive level.
Validation 2: EMC pre-test - near-field probe
- Near-field probe (H-field, 10 - 30 mm diameter) with spectrum analyser or Signalhound BB60C
- Scanning of the area via quartz, capacitors and IC
- Expectation: Fundamental frequency visible, clearly dominant. Harmonics attenuated.
Alarm signals: high harmonics (> 3rd order) or clear emissions at points away from the crystal indicate coupling and layout problems. (See also the case study https://www.petermann-technik.de/praxis-wissen/40mhz-quarz-emv-verbessern-fallbeispiel.html
Validation 3: VCC coupling strength
- Inject a noise injector or function generator into the VCC line (50 - 200 mVpp noise, bandwidth 10 kHz - 100 MHz)
- Observe frequency stability and jitter at the output
Expectation: Frequency changes by < 2 ppm, jitter remains within the specified range. Strong deflections indicate insufficient local VCC decoupling at the oscillator IC.
Validation 4: Cold start
- Climate chamber at -40 °C (or cold spray), VCC at Vmin
- At least 30 switch-on processes. Each must swing on safely (see post on start-up time)
Most common layout error that comes to light here: Cpar too high, causing |-Rneg| to fall below ESR in the worst case.
Validation 5: Temperature profile on the quartz housing
- Thermal imaging camera or thermocouple directly on the quartz housing
- Expectation: quartz housing < 5 K above ambient temperature
If the quartz heats up significantly (> 10 K), the drive level is too high - see post on drive level measurement. The consequences are accelerated ageing and drift.
Frequent layout errors and their measurement signature
| Layout errors | Typical measurement signature | Remedy |
|---|---|---|
| GND area under quartz | Frequency shift +5 to +20 ppm, Cpar > 4 pF | GND cut-out on all layers |
| Long leads (> 10 mm) | Jitter increased, start time extended | shorten routing, quartz closer to IC |
| C1/C2 placed asymmetrically | Different amplitudes at XIN/XOUT, drive level asymmetrical | Symmetrical routing |
| Clock line close to the quartz | Sidebands in the spectrum, increased phase jitter | Distance ≥ 5 mm, if necessary. GND conductor in between |
| No local blocking capacitor (100 nF) on IC VCC | Frequency drift with load changes | 100 nF + 10 nF as close as possible to the IC |
| Vias under quartz | Increased jitter, poor EMC | Via free space under quartz, adjust routing |
| Quartz housing pads floating | Sensitive to hand proximity, EMC coupling | Pads #2/#4 directly on GND |
Final design approval
We recommend a summarised test table before series approval. All points must be passed at the worst-case operating point (Vmin, -40 °C or +85 °C depending on the application, worst-case component tolerance):
| Test point | Target | Acceptance |
|---|---|---|
| Frequency accuracy at +25 °C, Vnom | ± < 5 ppm | Pass |
| Gain-Margin (|-Rneg| / ESR) Worst-Case | ≥ 3 (Industry) / ≥ 5 (Automotive) | Pass |
| Start-Up-Time Worst-Case | < 3× typical value at +25 °C | Pass |
| Drive level | ≤ 60% of the quartz data sheet value | Pass |
| Period jitter | < application request | Pass |
| Cpar from frequency method | within design assumption ±0.5 pF | Pass |
| EMV near-field check | no noticeable emissions except quartz useful frequency | Pass |
| Temperature cycle test 10 cycles -40/+85 °C | no start failures, no drift > 10 ppm | pass |
Layout best practice in three lines
The most important rules at a glance 1. Quartz + C1, C2 compact and directly on the IC, symmetrical routing, short lines. 2. No GND area and no signals under the crystal, dedicated GND island for the capacitors. 3. Housing pads #2/#4 on 4-pad ceramic crystals on GND - define this connection early on and do not change it later for frequency equalisation. |
Further information
The layout principles are described in the practical guide "Matching crystals optimally to ICs" (sections G and 6). This post supplements the guide with measurement-based validation on the finished board - from jitter check to worst-case acceptance.</p
<p>You have questions about implementation
Our frequency experts will support you in selecting the right crystal, taking measurements in your circuit and providing design-in support through to series release.
- Request technical advice
- Discuss your application with us
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- Request an alternative via cross reference
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