Layout validation on the finished board - check jitter, EMC and start-up behaviour

The metrological validation of a crystal layout on the finished board is carried out in a structured manner using several tests that reveal typical layout weaknesses. These include, in particular, the jitter measurement at the oscillator output, a preliminary EMC test with a near-field probe, the VCC coupling strength test, the cold start test and the temperature measurement directly on the crystal housing. Prior to these measurements, the layout should already be checked against established design rules so that obvious faults can be detected early on. It is crucial that all tests are also carried out at the worst-case operating point, i.e. at minimum supply voltage, critical temperature and component tolerances. Only when the board has fully passed this validation is there a reliable basis for series release.

In layout validation, jitter measurement is a key indicator of the quality of clock generation on the finished board. The site specifies a period jitter of less than 30 ps RMS as the expected value for standard applications, while less than 10 ps RMS is the target for demanding interfaces such as USB, Ethernet or HDMI. Increased jitter of over 50 ps RMS indicates layout problems such as coupling of neighboring signals, improper ground routing or a drive level that is too low. Measurements are taken at the output of the clock signal driven by the crystal oscillator, for example at the PLL output, SYSCLK pin or UART baud rate pin. For reliable results, an oscilloscope with a bandwidth of at least 1 GHz and a jitter analysis function for period jitter and cycle-to-cycle jitter should be used.

EMC problems in the crystal layout can be detected very well on the finished board using a near-field probe and a spectrum analyzer. The area above the crystal, load capacitors and oscillator IC is systematically scanned in order to make the local radiation visible. It is expected that the fundamental frequency clearly dominates and higher harmonics are clearly attenuated. If high harmonics above the third order or clear emissions occur at points away from the crystal, this indicates undesirable coupling and layout errors. Such measurement signatures help to specifically identify problems in the conductor routing, ground connection or decoupling.

Testing the VCC coupling strength shows how robust the oscillator circuit is designed to withstand interference on the supply voltage. For this purpose, noise with typically 50 to 200 mVpp and a bandwidth of 10 kHz to 100 MHz is coupled into the VCC line, while frequency stability and jitter are observed at the output. Ideally, the frequency changes by less than 2 ppm and the jitter remains within the specified limits. Large deviations indicate insufficient local VCC decoupling at the oscillator IC. This validation is particularly important because supply couplings frequently occur in real system operation and can directly influence the clock quality.

Typical weaknesses of a quartz layout become particularly apparent during the cold start test and temperature measurement. During the start test in the climatic chamber at -40 °C or with cold spray and at minimum supply voltage, the oscillator must oscillate reliably in at least 30 switch-on processes. If the oscillation does not occur or is unstable, the parasitic capacitance is often too high, so that the |-Rneg| reserve falls below the ESR value in the worst case. In addition, the temperature measurement on the quartz housing shows whether the drive level has been selected correctly. If the housing heats up by more than 5 K above ambient or even well above 10 K, the quartz is being driven too high, which can accelerate ageing and frequency drift.

PETERMANN-TECHNIK specializes in quartz crystals, oscillators and frequency-generating components and combines component know-how with practical measurement and layout expertise. The company not only provides support in selecting the right quartz crystal, but also with measurements directly in your circuit and with design-in support through to series release. This combination of theory and validation on the finished board is particularly valuable when it comes to issues such as jitter, EMC, VCC coupling strength and safe starting behavior. The structured approach helps to reliably identify critical layout errors before series production and to evaluate them in a technically sound manner. For industrial B2B applications, this means greater development reliability, lower risk in the field and a reliable release under worst-case conditions.