Practical measurement methods for the post "Optimising quartz crystals for ICs" - sections E and 4
To the encyclopaedia article : Matching crystals optimally to ICs
What it's all about:
The start-up time is the time between switching on the supply voltage (or enabling the oscillator in the MCU) and reaching a stable, usable oscillation. It is particularly critical for low-power MCUs with frequent sleep/wake cycles because each start process is directly included in the energy balance and determines the overall latency.
Typical requirements: < 2 ms for fast MCUs with a strong oscillator, 2 - 10 ms for standard designs, 250 - 1000 ms for 32.768 kHz clock crystals.
Influence variables
- Gain of the oscillator in the IC (|-Rneg|)
- ESR of the crystal
- Load capacitance CL or actually effective C1, C2 and Cpar
- Temperature (-40 °C significantly longer than +25 °C)
- Supply voltage (low VCC extends start time exponentially)
- Quality of the VCC ramp (rise time, monotony)
Definition of the start-up time
The start-up time is usually defined as the time at which the oscillation amplitude reaches 90% of its steady-state final value. Some MCU manufacturers define it differently as reaching the digital logic level or as enabling the XOSC ready flag.
| Definition | Measurement point | Typically used by |
|---|---|---|
| 90 % criterion | Oscilloscope to XOUT | Quartz manufacturer, laboratory practice |
| 95 % criterion | Oscilloscope to XOUT | Strict Automotive-Spec |
| Logic level at output | Clock output / GPIO | MCU data sheet |
| XOSC-Ready-Flag | Status register / GPIO toggle | MCU firmware view |
Measurement setup
Equipment
- Oscilloscope ≥ 500 MHz, ≥ 2 GS/s, deep memory depth (≥ 1 MPt)
- Active FET probe on XOUT (low input capacitance, ≤ 1 pF)
- Second channel on VCC (directly on the IC's supply pin)
- Optional: third channel on a GPIO that is toggled by the MCU startup code (e.g. for XOSC-Ready). e.g. for XOSC ready flag)
- Measurement tip with short ground reference (< 5 mm) to minimise ground inductance
Pass-through
- Triggering: edge on VCC (e.g. at 50 % of Vnom) or on the GPIO that marks the oscillator switch-on.
- Set time base to the expected start range - for MHz crystals typically 0.2 ms/div (total window 2 ms), for 32.768 kHz crystals typically 50 ms/div.
- Record at least 3 times the expected start time to capture the transient process completely.
- Evaluation: Determine the envelope of the XOUT oscillation. t_start is the time at which 90 % of the steady-state amplitude is reached.
- For series evaluation: Record 10 - 30 individual starts (persistence mode) and evaluate the longest start time as the worst case.
Important when triggering Do not trigger on the oscillation itself. The oscillator starts out of the noise, and triggering on any edge of the increasing amplitude systematically distorts the start time. Always trigger on the external event: VCC edge or GPIO pulse of the MCU startup code. |
Characterise start-up time via temperature and voltage
A single measurement at +25 °C and nominal voltage is insufficient. The following matrix is recommended for robust designs:
| Temperature | VCC | Measurement | Acceptance |
|---|---|---|---|
| +25 °C | Vnom | Reference | Base value |
| -40 °C | Vnom | Cold | < 3× base value |
| +85 °C | Vnom | Heat | < 1.5× base value |
| +25 °C | Vmin (-10 %) | Limit voltage | < 2× base value |
| -40 °C | Vmin | Worst-Case-Combination | < 5× base value |
| +25 °C | VCC ramp slow (5 ms) | monotonicity check | oscillation starts safely |
Interpretation of the envelope
The envelope of the starting oscillation normally follows an exponential function:
U(t) = U_rausch - exp( t / τ ) with τ = 2-L1 / (|-Rneg| - ESR)
Two anomalies provide valuable clues:
Plateau in the run-up (amplitude does not continue to grow, then suddenly does): Indicates borderline |-Rneg| reserve. Often at low temperatures or low VCC. Countermeasure: Quartz with lower ESR.
Overshoot of the amplitude (stationary value is briefly exceeded): Shows strong amplification, usually uncritical. However, may be accompanied by a brief increase in the drive level - check for ageing effects with very sensitive quartz crystals.
Typical measured values
| Quartz type | Oscillator | t_start (90 %) typ. |
|---|---|---|
| MHz standard SMD | Strong MCU-OSC | 0.3 - 1.5 ms |
| MHz Standard-SMD | Low-Power-MCU | 1 - 5 ms |
| MHz LRT quartz low ESR | low-power MCU | 0.5 - 2 ms |
| 32,768 kHz clock quartz | RTC oscillator | 250 - 800 ms |
| 32.768 kHz clock crystal, CL = 4 pF | Low-Power RTC | 500 - 1500 ms |
Improvement measures if the start time is too long
- Select crystal with significantly lower ESR (factor 2 - 3 compared to specification maximum)
- Reduce load capacitance if permitted by MCU (lower C1/C2 and thus CL_eff)
- Configure oscillator gain stage in MCU to "High Drive" / "Fast Start"
- Reduce layout parasitics (see post on parasitic capacitances)
- For clock crystals: In low-power applications, favour LRT technology to keep start time and start-up reserve safe even at low VCC
Further information
The correlations between start time, ESR, gain and temperature are described in the practical guide "Optimally matching crystals to ICs" (sections E and 4). This post provides the measurement practice for this - from the trigger strategy to temperature characterisation.
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