Practical measurement methods for the post "Optimising quartz crystals for ICs" - sections C and 5
To the encyclopaedia article : Matching crystals optimally to ICs
What it's all about:
The two external circuit capacitors C1 and C2 on the Pierce oscillator together with the parasitic capacitances of the circuit (stray) determine the effective load capacitance. A simple formula value from the data sheet is usually not sufficient because each circuit board has an individual stray. This post shows how C1 and C2 are correctly dimensioned and verified in the circuit.
Initial formula for dimensioning
For symmetrical wiring (C1 = C2 = CX) the following applies:
CL = CX / 2 + Cstray ⇒ CX = 2 - (CL - Cstray)
The following rule of thumb is given as the starting value in many data sheets (CL and CX in pF):
CX = 2 - CL - 2 - Cstray (Cstray typ. 2 pF)
From the original article, the following results for CL = 12 pF: 2-12 - 2-2 = 20 pF. With an average stray of 2 pF, the calculation example in the lexicon (18 pF per side) leads to the identical effective operating point - depending on the actual pin capacitance of the IC.
Step 1: Calculate starting value from data sheet
Dimensioning always starts with two data sheet values:
- CL of the crystal (e.g. 8 pF, 12 pF, 16 pF, 20 pF)
- Capacitive load of the IC at XIN/XOUT (usually 1 - 7 pF per pin; usually specified in the MCU data sheet as "CIN/COUT" or "CLoad")
| Quartz-CL | Cstray (typ.) | CX start value C1/C2 | Range |
|---|---|---|---|
| 6 pF | 2 pF | 8 pF | 7 - 12 pF |
| 8 pF | 2 pF | 12 pF | 10 - 15 pF |
| 10 pF | 2 pF | 16 pF | 15 - 18 pF |
| 12 pF | 2 pF | 20 pF | 18 - 22 pF |
| 12.5 pF | 2 pF | 21 pF | 18 - 22 pF |
| 16 pF | 2 pF | 28 pF | 22 - 30 pF |
| 20 pF | 2 pF | 36 pF | 33 - 39 pF |
Important before dimensioning Check the MCU data sheet to see what pin capacity the manufacturer specifies for XIN/XOUT. Some modern low-power MCUs deliberately have increased pin capacitances of up to 7 pF, others only 1-2 pF. Calculate with the actual value, not the rule of thumb. | |||
Step 2: Determine the stray of the PCB (variation method)
On the target board, Cstray is determined by two frequency measurements at different C1/C2 values. This is the simplest and most reliable laboratory method.</p
<h3 class="text-justify">Measurement setup
Two sets of C0G/NP0 capacitors (±2 %) of significantly different values, e.g. 10 pF and 22 pF
Frequency counter ≥ 0.1 ppm resolution with external reference
Low-capacitance FET probe (< 1 pF)
Implementation
Fitting 1: C1 = C2 = C_A (e.g. 10 pF) → measure frequency f_A.
Fitting 2: C1 = C2 = C_B (e.g. 22 pF) → measure frequency f_B.
Express both frequencies as a deviation from the nominal frequency: Δf_A, Δf_B in ppm.
Determine the stray from the system of equations.
Calculating equation
From the two measurements, the pull sensitivity S and the parasitic capacitance Cstray follow:
S = (Δf_B - Δf_A) / (CL_B_eff - CL_A_eff) [ppm/pF]
Where CL_eff = CX/2 + Cstray. Equating the specified pull sensitivity (from the crystal data sheet) and resolving according to Cstray results in a unique value. In practice, developers usually use a small Excel spreadsheet or an MCU manufacturer app for this purpose.
Step 3: In-circuit measurement of the effective capacitance
Very elegant and without soldering: The capacitance between XIN (or XOUT) and GND is measured with a precise LCR meter when switched off.
Measurement procedure
- Supply voltage to 0 V, circuit completely de-energised.
- Desolder (or do not equip) the crystal - only C1, C2, IC pin and traces in the measurement path.
- Measure the capacitance XIN → GND and XOUT → GND with an LCR meter (1 MHz measurement signal, ≤ 100 mV).
- Measured values should correspond to the calculated CX values + 1...3 pF (IC pin).
Caution with the LCR measurement The IC pin capacitance is voltage-dependent. The LCR measurement in the switched-off state therefore does not provide the exact operating value. For precision designs, the frequency method (step 2) is the more reliable reference. |
Step 4: Check symmetry
Unbalanced wiring (C1 ≠ C2) worsens the starting behaviour and drive level distribution. In practice, we recommend:
| Parameters | Target value | Boundary value |
|---|---|---|
| Deviation C1 to C2 | ≤ 2 % | ≤ 5 % |
| Tolerance C0G (NP0) | ±2 % | ±5 % |
| Tolerance standard ceramic X7R | not recommended | - |
| Voltage coefficient | ≤ 1 % at Voperation | - |
Example calculation using the variation method
Quartz: 24,000 MHz, CL = 8 pF, pull sensitivity S = -20 ppm/pF (from data sheet).
| Population | C1 = C2 | measured frequency | Δf/f |
|---|---|---|---|
| Measurement A | 10 pF | 24,000 042 MHz | +1.75 ppm |
| Measurement B | 22 pF | 23.999 928 MHz | -3.00 ppm |
Between the two placements, CX/2 changes by (22-10)/2 = 6 pF. The measured frequency change is -4.75 ppm → S_measured = -0.79 ppm/pF - (1/6) = actually around -19.8 ppm/pF, matches the data sheet.
With Δf_A = +1.75 ppm at CX = 10 pF: CL_eff_A = 10/2 + Cstray = 5 + Cstray. From Δf = S - (CL_eff - CL_spec) follows CL_eff_A ≈ 8 - (1.75/-20) = 7.91 pF → Cstray ≈ 2.9 pF.
Result: The circuit board has Cstray ≈ 2.9 pF. Target value CX = 2-(8 - 2.9) = 10.2 pF. An assembly with 10 pF ±2 % is therefore almost exactly on target.
Further information
The formulas and the relationship between CL, C1/C2 and Cstray are explained in the practical guide "Optimally matching quartz crystals to ICs" (sections B, C and 5). This post shows the laboratory measurement with which the calculation is compared on your real PCB.
You have questions about the implementation
Our frequency experts will support you in selecting the right quartz, with measurements in your circuit and with design-in support through to series release.
- Request technical advice
- Discuss your application with us
- Define and order a sample crystal
- Request an alternative via cross reference
Phone: +49 8191 305395 Email: info@petermann-technik.de
Your success is our goal.
