Practical measurement methods for the post "Optimising quartz crystals for ICs" - sections C and 5
To the encyclopaedia article : Matching crystals optimally to ICs
What it's all about:
The two external circuit capacitors C1 and C2 on the Pierce oscillator together with the parasitic capacitances of the circuit (stray) determine the effective load capacitance. A simple formula value from the data sheet is usually not sufficient because each circuit board has an individual stray. This post shows how C1 and C2 are correctly dimensioned and verified in the circuit.
Initial formula for dimensioning
For symmetrical wiring (C1 = C2 = CX) the following applies:
CL = CX / 2 + Cstray ⇒ CX = 2 - (CL - Cstray)
The following rule of thumb is given as the starting value in many data sheets (CL and CX in pF):
CX = 2 - CL - 2 - Cstray (Cstray typ. 2 pF)
From the original article, the following results for CL = 12 pF: 2-12 - 2-2 = 20 pF. With an average stray of 2 pF, the calculation example in the lexicon (18 pF per side) leads to the identical effective operating point - depending on the actual pin capacitance of the IC.
Step 1: Calculate starting value from data sheet
Dimensioning always starts with two data sheet values:
- CL of the crystal (e.g. 8 pF, 12 pF, 16 pF, 20 pF)
- Capacitive load of the IC at XIN/XOUT (usually 1 - 7 pF per pin; usually specified in the MCU data sheet as "CIN/COUT" or "CLoad")
| Quartz-CL | Cstray (typ.) | CX start value C1/C2 | Range |
|---|---|---|---|
| 6 pF | 2 pF | 8 pF | 7 - 12 pF |
| 8 pF | 2 pF | 12 pF | 10 - 15 pF |
| 10 pF | 2 pF | 16 pF | 15 - 18 pF |
| 12 pF | 2 pF | 20 pF | 18 - 22 pF |
| 12.5 pF | 2 pF | 21 pF | 18 - 22 pF |
| 16 pF | 2 pF | 28 pF | 22 - 30 pF |
| 20 pF | 2 pF | 36 pF | 33 - 39 pF |
Important before dimensioning Check the MCU data sheet to see what pin capacity the manufacturer specifies for XIN/XOUT. Some modern low-power MCUs deliberately have increased pin capacitances of up to 7 pF, others only 1-2 pF. Calculate with the actual value, not the rule of thumb. | |||
Step 2: Determine the stray of the PCB (variation method)
On the target board, Cstray is determined by two frequency measurements at different C1/C2 values. This is the simplest and most reliable laboratory method.</p
<h3 class="text-justify">Measurement setup
Two sets of C0G/NP0 capacitors (±2 %) of significantly different values, e.g. 10 pF and 22 pF
Frequency counter ≥ 0.1 ppm resolution with external reference
Low-capacitance FET probe (< 1 pF)
Implementation
Fitting 1: C1 = C2 = C_A (e.g. 10 pF) → measure frequency f_A.
Fitting 2: C1 = C2 = C_B (e.g. 22 pF) → measure frequency f_B.
Express both frequencies as a deviation from the nominal frequency: Δf_A, Δf_B in ppm.
Determine the stray from the system of equations.
Calculating equation
From the two measurements, the pull sensitivity S and the parasitic capacitance Cstray follow:
S = (Δf_B - Δf_A) / (CL_B_eff - CL_A_eff) [ppm/pF]
Where CL_eff = CX/2 + Cstray. Equating the specified pull sensitivity (from the crystal data sheet) and resolving according to Cstray results in a unique value. In practice, developers usually use a small Excel spreadsheet or an MCU manufacturer app for this purpose.
Step 3: In-circuit measurement of the effective capacitance
Very elegant and without soldering: The capacitance between XIN (or XOUT) and GND is measured with a precise LCR meter when switched off.
Measurement procedure
- Supply voltage to 0 V, circuit completely de-energised.
- Desolder (or do not equip) the crystal - only C1, C2, IC pin and traces in the measurement path.
- Measure the capacitance XIN → GND and XOUT → GND with an LCR meter (1 MHz measurement signal, ≤ 100 mV).
- Measured values should correspond to the calculated CX values + 1...3 pF (IC pin).
Caution with the LCR measurement The IC pin capacitance is voltage-dependent. The LCR measurement in the switched-off state therefore does not provide the exact operating value. For precision designs, the frequency method (step 2) is the more reliable reference. |
Step 4: Check symmetry
Unbalanced wiring (C1 ≠ C2) worsens the starting behaviour and drive level distribution. In practice, we recommend:
| Parameters | Target value | Boundary value |
|---|---|---|
| Deviation C1 to C2 | ≤ 2 % | ≤ 5 % |
| Tolerance C0G (NP0) | ±2 % | ±5 % |
| Tolerance standard ceramic X7R | not recommended | - |
| Voltage coefficient | ≤ 1 % at Voperation | - |
Example calculation using the variation method
Quartz: 24,000 MHz, CL = 8 pF, pull sensitivity S = -20 ppm/pF (from data sheet).
| Population | C1 = C2 | measured frequency | Δf/f |
|---|---|---|---|
| Measurement A | 10 pF | 24,000 042 MHz | +1.75 ppm |
| Measurement B | 22 pF | 23.999 928 MHz | -3.00 ppm |
Between the two placements, CX/2 changes by (22-10)/2 = 6 pF. The measured frequency change is -4.75 ppm → S_measured = -0.79 ppm/pF - (1/6) = actually around -19.8 ppm/pF, matches the data sheet.
With Δf_A = +1.75 ppm at CX = 10 pF: CL_eff_A = 10/2 + Cstray = 5 + Cstray. From Δf = S - (CL_eff - CL_spec) follows CL_eff_A ≈ 8 - (1.75/-20) = 7.91 pF → Cstray ≈ 2.9 pF.
Result: The circuit board has Cstray ≈ 2.9 pF. Target value CX = 2-(8 - 2.9) = 10.2 pF. An assembly with 10 pF ±2 % is therefore almost exactly on target.
Further information
The formulas and the relationship between CL, C1/C2 and Cstray are explained in the practical guide "Optimally matching quartz crystals to ICs" (sections B, C and 5). This post shows the laboratory measurement with which the calculation is compared on your real PCB.
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FAQs
How are the external capacitances C1 and C2 on the Pierce oscillator correctly dimensioned?
The dimensioning of C1 and C2 depends on the required load capacitance CL of the quartz and the parasitic capacitance Cstray of the real circuit. For symmetrical wiring with C1 = C2 = CX, the relationship CL = CX / 2 + Cstray applies, resulting in CX = 2 - (CL - Cstray). A pure data sheet value is often not sufficient in practice because the PCB, IC pins and layout also influence the effective load capacitance. A typical Cstray of around 2 pF is often used as a starting value, but the actual design should be verified on the target board. This allows the crystal to be operated closer to its specified operating point and improves the frequency accuracy.
Why is Cstray so important in the design of quartz circuit capacitors?
Cstray describes the parasitic capacitances of the circuit, which act on the load capacitance of the quartz in addition to the external capacitors C1 and C2. These include the input capacitances of XIN and XOUT, trace capacitances and layout influences. If Cstray is not correctly taken into account, the effective load capacitance and therefore also the oscillator frequency will shift. This is precisely why a purely theoretical calculation from the data sheet is not sufficient in many cases. Only by taking the actual PCB into account is it possible to design a reliable crystal circuit.
How can the parasitic capacitance Cstray on the PCB be reliably determined?
A simple and reliable laboratory method is the variation method with two different symmetrical configurations for C1 and C2. For example, 10 pF and 22 pF C0G/NP0 capacitors are used and the resulting frequency deviation from the nominal frequency is measured in ppm. Cstray can be clearly determined from the two measuring points and the pull sensitivity of the crystal from the data sheet. Alternatively, the capacitance between XIN or XOUT and GND can be measured in a de-energized state using a precise LCR meter. Both methods help to better capture the real load capacitance of the circuit and to adjust the capacitor values in a targeted manner.
Which measuring equipment and components are required for the determination of Cstray and the verification of C1/C2?
Two sets of high-quality C0G/NP0 capacitors with significantly different values are required for the variation method, for example 10 pF and 22 pF. In addition, a frequency counter with a resolution of at least 0.1 ppm and an external reference is useful for reliably recording small frequency changes. For measurements on the oscillator, a low-capacitance FET probe with less than 1 pF should be used so that the circuit is not unnecessarily loaded. A precise LCR meter, ideally with a 1 MHz measurement signal and low measurement voltage, is suitable for in-circuit testing of the capacitance. With this equipment, the calculation and real behavior of the quartz circuit can be cleanly compared with each other.
Why should the crystal circuit be as symmetrical as possible with C1 = C2?
A symmetrical circuit with the same values for C1 and C2 ensures a defined and easily calculable load capacitance on the Pierce oscillator. This allows the formula for the design to be applied directly and simplifies tuning to the specified CL of the quartz crystal. Unbalanced circuits with C1 ≠ C2 can worsen the starting behavior and have an unfavorable effect on the distribution of the drive level. This can have a negative effect on the stability, frequency response and reliability of the oscillator. In practice, a symmetrical design is therefore the preferred solution in most cases.
Why PETERMANN-TECHNIK dimension external capacitances C1/C2 and determine Cstray?
PETERMANN-TECHNIK supports developers in the precise design of crystal circuits on real PCBs, combining data sheet knowledge with practical measurement technology. This is particularly important because C1, C2 and Cstray together determine the effective load capacitance and therefore the actual frequency. The company supports customers in the selection of the right quartz, in measurements in the circuit and in verification up to series release. This application-oriented support reduces mismatches, unnecessary iterations and frequency deviations in the design process. For industrial B2B applications, PETERMANN-TECHNIK is therefore a competent partner for resilient, frequency-stable oscillator solutions.
